W25Q64DWZEIG【PDF 25/82 页】IC FLASH SPI 64MBIT 8WSON

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W25Q64DW

/CS

Mode 3

CLK

Mode 0

In structio n

05h or 35h

IO 0

IO 1

IO 2

IO 3

SR1 or SR2 SR1 or SR2

out

Figure 8b. Read Status Register Instruction (QPI Mode)

10.2.10 Write Status Register (01h)

The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status

LB1, LB0, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit

locations are read-only and will not be affected by the Write Status Register instruction. LB3-0 are non-

volatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in

Figure 4a and 4b, and described in 10.1.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have

been executed for the device to accept the Write Status Register instruction (Status Register bit WEL

must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction

code “01h”, and then writing the status register data byte as illustrated in figure 9.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must

have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).

However, SRP1 and LB3, LB2, LB1, LB0 can not be changed from “1” to “0” because of the OTP

protection for these bits. Upon power off or the execution of a “Reset (99h)” instruction, the volatile Status

To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or

sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be

executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE and

SRP1 bits will be cleared to 0.

During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the

self-timed Write Status Register cycle will commence for a time duration of t W (See AC Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be

accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle

Publication Release Date: September 18, 2012

- 25 -

Revision D

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